# Auto generated by Edalize
NAME := {{ name }}
OPTIONS := {{ tool_options.quartus_options|join(' ') }}
DSE_OPTIONS := {{ tool_options.dse_options|join(' ') }}

all: sta

project: $(NAME).tcl
	$(EDALIZE_LAUNCHER) quartus_sh $(OPTIONS) -t $(NAME).tcl

qsys: project
{% for qsys_file in src_files if qsys_file|qsys_file_filter %}
	qsys-generate {{ qsys_file|qsys_file_filter }} --synthesis=VERILOG --family="{{ tool_options.family }}" --part={{ tool_options.device }} --quartus-project=$(NAME)
{% endfor %}

syn: qsys
	$(EDALIZE_LAUNCHER) quartus_syn $(OPTIONS) $(NAME)

fit: syn
	$(EDALIZE_LAUNCHER) quartus_fit $(OPTIONS) $(NAME)

asm: fit
	$(EDALIZE_LAUNCHER) quartus_asm $(OPTIONS) $(NAME)

sta: asm
	$(EDALIZE_LAUNCHER) quartus_sta $(OPTIONS) $(NAME)

dse: syn
	$(EDALIZE_LAUNCHER) quartus_dse $(NAME) $(DSE_OPTIONS)

clean:
	$(EDALIZE_LAUNCHER) rm -rf *.* qdb tmp-clearbox

.PHONY: all project qsys syn fit asm sta dse clean
