# Auto generated by Edalize
NAME := {{ name }}
OPTIONS := {{ tool_options.quartus_options|join(' ') }}
DSE_OPTIONS := {{ tool_options.dse_options|join(' ') }}

all: sta

project: $(NAME).tcl
	$(EDALIZE_LAUNCHER) quartus_sh $(OPTIONS) -t $(NAME).tcl

qsys: project
{% for qsys_file in src_files if qsys_file|qsys_file_filter %}
	$(EDALIZE_LAUNCHER) ip-generate --project-directory={{qsys_file.srcdir}} --output-directory={{qsys_file.dstdir}} --report-file=bsf:{{qsys_file.dstdir}}/{{qsys_file.simplename}}.bsf --system-info=DEVICE_FAMILY="{{tool_options.family}}" --system-info=DEVICE={{tool_options.device}} --component-file={{qsys_file.srcdir}}/{{qsys_file.simplename}}.qsys
	$(EDALIZE_LAUNCHER) ip-generate --project-directory={{qsys_file.srcdir}} --output-directory={{qsys_file.dstdir}}/synthesis --file-set=QUARTUS_SYNTH --report-file=sopcinfo:{{qsys_file.dstdir}}/{{qsys_file.simplename}}.sopcinfo --report-file=html:{{qsys_file.dstdir}}/{{qsys_file.simplename}}.html --report-file=qip:{{qsys_file.dstdir}}/{{qsys_file.simplename}}.qip --report-file=cmp:{{qsys_file.dstdir}}/{{qsys_file.simplename}}.cmp --report-file=svd --system-info=DEVICE_FAMILY="{{tool_options.family}}" --system-info=DEVICE={{tool_options.device}} --component-file={{qsys_file.srcdir}}/{{qsys_file.simplename}}.qsys --language=VERILOG
{% endfor %}

syn: qsys
	$(EDALIZE_LAUNCHER) quartus_map $(OPTIONS) $(NAME)

fit: syn
	$(EDALIZE_LAUNCHER) quartus_fit $(OPTIONS) $(NAME)

asm: fit
	$(EDALIZE_LAUNCHER) quartus_asm $(OPTIONS) $(NAME)

sta: asm
	$(EDALIZE_LAUNCHER) quartus_sta $(OPTIONS) $(NAME)

dse: syn
	$(EDALIZE_LAUNCHER) quartus_dse $(NAME) $(DSE_OPTIONS)

clean:
	$(EDALIZE_LAUNCHER) rm -rf *.* db incremental_db

.PHONY: all project qsys syn fit asm sta dse clean
